1. Field of the Invention
The embodiments of the invention provide a method, computer program product, etc. for yield optimization in router for systematic defects.
2. Description of the Related Art
In the design and manufacture of semiconductor chips, two yield detractors in the manufacturing process are random defects and systematic defects. Random defects refer to electrical faults (e.g., opens and shorts) caused by foreign material or impurities. Systematic defects—also known as process-sensitive sites—constitute electrical faults that arise because of the inherent difficulty of reliably building certain structures in a given manufacturing technology.
Systematic defects are seen in wafer processing lines. During the early life of a manufacturing line, systematic defects are a larger yield detractor than random defects. Design related systematic layout issues are observed when product reaches test. In some cases, product is redesigned to improve yield, but in many cases redesign is not possible because of customer impact. It is desirable to have routers consider systematic defects. Systematic yield sensitivity needs to be traded off with sensitivity to random defects to create the most cost effective option for the product.
Critical-area computation is known (e.g., dot-throwing, geometric expansion, Voronoi diagrams), but currently, there are no methods that use critical area analysis assessment with random defects and identification of systematic defects to optimize yield